1. Field of the Invention
An aspect of this disclosure relates to a semiconductor integrated circuit, a switching power supply including the semiconductor integrated circuit, and a control system including the switching power supply.
2. Description of the Related Art
FIG. 1 is a circuit diagram of a step-down switching regulator 100 provided as an example of a switching power supply. The step-down switching regulator 100 is a DC-DC converter that steps down an input voltage VB supplied from an external power supply 1 connected to a pair of power input terminals 2 and 3 and thereby regulates an output voltage VOUT to be output from an output terminal 10 to a target voltage level. The step-down switching regulator 100 includes an input capacitor 4 for smoothing the input voltage VB, a semiconductor integrated circuit 20 including a high-side drive transistor 24 and a low-side drive transistor 25, an inductor 6 whose one end is connected to a node between the high-side drive transistor 24 and the low-side drive transistor 25 and the other end is connected to the output terminal 10, and an output capacitor 9 that is supplied with energy stored in the inductor 6 and smoothes the output voltage VOUT. The drive transistor 24 and/or the drive transistor 25 may be implemented by a semiconductor switching device such as a MOSFET or a bipolar transistor.
The semiconductor integrated circuit 20 also includes a reference voltage generating circuit 21, an oscillator 22, a PWM drive circuit 23, and an error amplifier 26. The PWM drive circuit 23 drives the drive transistors 24 and 25, which in turn drive the inductor 6, using pulse-width modulation according to a synchronous rectification method based on a periodic signal from the oscillator 22 and an amplified-error signal from the error amplifier 26. The PWM drive circuit 23 thereby steps down the input voltage VB supplied from a power supply terminal 27 with respect to a ground terminal 29 to a target voltage level and outputs the stepped-down (regulated) voltage as the output voltage VOUT from the output terminal 10. The error amplifier 26 amplifies the difference between a reference voltage VREF and a feedback voltage VFB. The reference voltage VREF is generated based on the input voltage VB by the reference voltage generating circuit 21 and is smoothed by a capacitor 5 connected to a reference voltage terminal 28. The feedback voltage VFB is obtained by dividing the output voltage VOUT with resistors 7 and 8 and input from a feedback terminal 31.
FIG. 2 is a cut-away side view of the semiconductor integrated circuit 20. The semiconductor integrated circuit 20 includes a P-type semiconductor substrate 41 where an n-type well 42 is formed. An n+-type source region 44 and an n+-type drain region 47 are formed in the n-type well 42. Also, a gate oxide film 45 is formed between the source region 44 and the drain region 47. Thus, the semiconductor integrated circuit 20 of FIG. 2 includes an N-channel MOSFET with a source electrode formed in the source region 44, a drain electrode 53 formed in the drain region 47, and a gate electrode 52 formed in the gate oxide film 45.
Assuming that the N-channel MOSFET corresponds to the low-side drive transistor 25 of FIG. 1, the source region 44 is connected to the ground and the drain electrode 53 is connected to a switch terminal 30 shown in FIG. 1. In this case, the drain electrode 53 corresponds to the node between the drive transistor 24 and the drive transistor 25.
With this configuration, when the drive transistor 24 is turned off, a potential VDB at the drain electrode 53 momentarily drops to a negative potential as illustrated in FIG. 3. Here, a parasitic element 56 is formed as an NPN bipolar transistor where the emitter is implemented by the n+-type drain region 47, the base is implemented by the P-type semiconductor substrate 41, and the collector is implemented by an n+-region 49 of another element (or transistor) formed on the P-type semiconductor substrate 41 of the semiconductor integrated circuit 20. When the potential VDB momentarily drops, the parasitic element 56 draws a current from the n+-region 49 to the P-type semiconductor substrate 41.
This behavior or operation of the parasitic element 56 causes a potential VDA at a drain electrode 54 formed in the n+-region 49 to drop as illustrated in FIG. 3. This in turn may cause the other element using the n+-region 49 and a circuit including the other element to malfunction. In a known technology, a guard ring is used to prevent the above described behavior or operation of a parasitic element and thereby to prevent malfunction (see, for example, Japanese Laid-Open Patent Publication No. 2001-77682).
As described above, the behavior or operation of a parasitic element formed in a semiconductor integrated circuit may destabilize the operation of another circuit formed in the semiconductor integrated circuit. One example of such a circuit destabilized by a parasitic element is a reference voltage generating circuit.
FIG. 4 is a circuit diagram of a reference voltage generating circuit 21A. The reference voltage generating circuit 21A is an example of the reference voltage generating circuit 21 of FIG. 1, and its configuration is disclosed, for example, in Japanese Laid-Open Patent Publication No. 11-65690 and Japanese Laid-Open Patent Publication No. 2006-313438. The reference voltage generating circuit 21A includes a pair of transistors 63 and 65 constituting a current mirror that receives an input current and outputs an output current with a value different from the value of the input current according to a predetermined input-output ratio, and an output transistor 67 that generates a reference voltage VREF according to the output current from the current mirror. In FIG. 4, it is assumed that the collector current of the transistor 65 is N times greater than the collector current of the transistor 63, and a current I flows through a parasitic transistor 68 whose collector is implemented by the collector region of the transistor 63. In this case, a current N×I flows through a parasitic transistor 69 whose collector is implemented by the collector region of the transistor 65. This mechanism is described below with reference to FIG. 5.
FIG. 5 is a drawing illustrating a configuration of a related-art semiconductor integrated circuit including a pair of transistors 63 and 65 constituting a current mirror that outputs an output current with a value different from that of an input current according to a predetermined input-output ratio. In FIG. 5, it is assumed that the collector current of the transistor 65 is two times greater than the collector current of the transistor 63 (i.e., N=2). When a transistor (e.g., the high-side drive transistor 24 in FIG. 1) connected to a drain electrode 53 is driven and a potential VDB of the drain electrode 53 drops to a negative potential, a parasitic element 94 formed as an NPN bipolar transistor operates and causes a parasitic current to flow. When a parasitic current with a current value I flows from an n+-type collector region 85 of the transistor 63 through a P-type semiconductor substrate 81 to an n+-type drain region 47, a parasitic current with a current value 2×I flows from collector regions 82 and 88 of the transistor 65 through the P-type semiconductor substrate 81 to the drain region 47. This is because the total area of the collector regions 82 and 88 of the transistor 65 is twice the area of the collector region 85 of the transistor 63.
The parasitic currents disrupt the balance of operating currents of the current mirror formed by the transistors 63 and 65. As a result, the reference voltage VREF generated by the output transistor 67 of FIG. 4 deviates from a target value (designed value).
Such unstable operation of a reference voltage generating circuit may lead to unstable operation (e.g., deviation of an output voltage VOUT) of a switching power supply that uses a reference voltage VREF generated by the reference voltage generating circuit. This may further lead to unstable operation (e.g., detection of an abnormal output voltage VOUT) of a control system that uses the output voltage VOUT generated by the switching power supply.